An apparatus capable of using a large amount of memory has been pursued to overcome a refresh limit for a DRAM (Dynamic Random Access Memory). Such an apparatus, for example, a ferroelectric random access memory (FRAM), has been developed by applying a ferroelectric thin layer to a dielectric layer of a capacitor. The FRAM, which uses a ferroelectric thin layer, is a nonvolatile memory device that retains storage information when power is interrupted, has high-speed access, low power consumption and resistance against collision. Such a ferroelectric memory is typically used as a main memory device or a recording medium in various electronic equipment having file storage and detection functions such as portable computers, cellular phones, gaming devices, etc.
In the ferroelectric memory device, a memory cell, which includes a ferroelectric capacitor and an access transistor, stores logic data ‘1’ or ‘0’ in accordance with an electric polarization state of the ferroelectric capacitor. For example, when a voltage is applied to both ends of the ferroelectric capacitor, a ferroelectric material is polarized according to a direction of an electric field. A switching threshold voltage to which a polarization state of the ferroelectric material is changed is called a coercive voltage. To read data stored in the memory cell, a voltage is applied to generate a potential difference between both electrodes of the ferroelectric capacitor, and a state of the data stored in the memory cell is sensed by a change of a charge amount excited to a bit line.
Referring to FIG. 1, when a ground voltage, for example, Vss or 0V, is applied to a ferroelectric material and an electric field is not applied to the ferroelectric material, the ferroelectric material is not polarized. When a voltage at both ends of a ferroelectric capacitor increases in a positive direction, a polarization level or charge amount thereof increases from zero to a state point A within a positive polarization region. At the state point A, a polarization is generated in one direction and a polarization level of the state point A reaches a maximum value. At this time, a polarization level, for example, a charge amount remaining in the ferroelectric material, is indicated by +Qs. If the voltage at both ends of the capacitor is reduced to the ground voltage Vss, the polarization level is not reduced to zero but instead remains at a state point B. A charge amount remaining in the ferroelectric material, for example, a residual polarization level, is indicated by +Qr.
Next, if the voltage at both ends of the capacitor increases in a negative direction, the polarization level is changed from the state point B to a state point C within a negative charge polarization region. At the state point C, the ferroelectric material is polarized in a direction opposite the polarization direction of the state point A. This polarization level is indicated by −Qs. If the voltage at both ends of the capacitor again falls to the ground voltage Vss, the polarization level does not fall to zero, but instead remains at a state point D. This residual polarization level is indicated by −Qr. When a magnitude of the voltage applied to both ends of the capacitor again increases in a positive direction, the polarization level of the ferroelectric material is changed from the state point D to the state point A.
FIG. 2 illustrates a memory cell of a memory cell array in a general ferroelectric memory device. As shown in FIG. 2, the memory cell is composed of an access transistor N1 and a ferroelectric capacitor C1. The access transistor N1 has a source terminal and a drain terminal, which are connected between an electrode of the ferroelectric capacitor C1 and a bit line BL, and a gate terminal connected to a word line WL. One electrode of the ferroelectric capacitor C1 is connected to the access transistor N1 and the other electrode is connected to a plate line PL.
As described above with reference to FIG. 1, when a voltage for generating an electric field is applied to a ferroelectric capacitor into which a ferroelectric material was inserted between its two electrodes, a polarization direction based on a spontaneous polarization is maintained even if the electrodes are in a floating state. A surface charge of the ferroelectric material based on the spontaneous polarization is not spontaneously lost due to leakage. If a voltage is not applied to the ferroelectric capacitor in an opposite direction to bring the polarization level to zero the polarization direction remains intact.
When a voltage applied to the ferroelectric capacitor in a positive direction is removed, a residual polarization of the ferroelectric material goes to a sate indicated by +Qr. In addition, when a voltage applied to the ferroelectric capacitor in a negative direction is removed, the residual polarization of the ferroelectric material goes to a state indicated by −Qr. Assuming that the residual polarization has the +Qr state at the state point B, and its logic state indicates data ‘0’, then when the residual polarization has a −Qr state at the state point D, its logic state indicates data ‘1’. Thus, a difference in a charge amount when changing from the state point A to the state point B (as indicated by voltage dQ0) is discriminated from a difference in a charge amount when changing from the state point D to the state point A (as indicated by voltage dQ1), and data stored in the memory cell is read.
To read data stored in the memory cell a specific reference voltage generating apparatus for generating a reference voltage having a voltage value at a mid level between a bit line voltage value for reading data ‘1’ and a bit line voltage value for reading data ‘0’ is needed to sense and amplify a voltage change excited to a bit line.
FIG. 3 illustrates a timing diagram for reading data from a main memory cell in a ferroelectric memory device having a conventional reference voltage generating apparatus.
Referring to FIG. 3, when a read operation starts, sense amplifier and complementary sense amplifier path signals SA_PATH and RSA_PATH are enabled and bit line pairs are connected to corresponding sense amplifiers. Before the read operation, main bit line and sub bit line precharge signals BL_PR and RBL_PR are enabled, precharging bit lines, a main bit line BL connected to the memory cell, and a sub bit line BLB connected to a reference cell. Then, at the same time as the start of the read operation, the main bit line and sub bit line precharge signals BL_PR and RBL_PR are disabled. A selected word line SWL0 and reference word line RSWL1 are enabled, a plate line voltage is applied to a plate line PL, and a reference plate line voltage is applied to reference plate lines RPL. Subsequently, a voltage data “1” or data “0” corresponding to data of a selected main memory cell is provided to the main bit line BL, and a reference voltage is provided to the sub bit line BLB connected to the reference cell. Then, a sense amplifier senses a voltage difference of the bit lines BL and BLB in response to a sense amplifier enable signal SAEN. When data reading is completed by the sense amplifier, the main memory cell is restored to its first data state in conformity with the read data. After the sense amplifier enable signal SAEN is applied, the complementary sense amplifier path signal RSA_PATH is disabled cutting off the sense amplifier and the sub bit line BLB, enabling the sub bit line precharge signal RBL_PR and grounding the sub bit line BLB, thereby preventing a data reverse effect for a selected reference cell.
Current methods for generating a reference voltage in a ferroelectric memory device are directed to applying a paraelectric capacitor or a ferroelectric capacitor to a reference cell. The method of applying a paraelectric capacitor having a small dielectric constant in a highly integrated memory device affects chip size because the capacitor takes up a large area. The method of applying a ferroelectric capacitor is divided into two methods. The first method uses a capacitance of a non-switching area of a hysteresis curve shown in FIG. 1. For example, the dQ0 value, is used as a reference voltage for controlling the size of the ferroelectric capacitor. The second method uses all switching capacitances and non-switching capacitances of the hysteresis curve of FIG. 1. Such methods enable the development of reduced chip sizes, but do not always supply a stabilized reference voltage having a typical ferroelectric characteristic. Thus, reducing the reliability of a memory device including the ferroelectric capacitor.
FIGS. 4 and 5 illustrate characteristic changes when using a non-switching capacitance of a ferroelectric capacitor in a reference cell. FIG. 4 illustrates a relaxation effect and FIG. 5 illustrates an imprint effect.
With reference to FIG. 4, the relaxation effect occurs when an electric field is removed from a ferroelectric capacitor having data preserved therein for a long time, e.g., for several milliseconds or more. As shown in FIG. 4, a polarization value is reduced from a state point B to a state point E at the hysteresis curve of the ferroelectric capacitor. If the relaxation effect produces a level difference in a semiconductor device, a capacitance change arises in a non-switching area causing a reference voltage level change and failure of the device.
As shown in FIG. 5, the imprint effect occurs when a ferroelectric capacitor remains in a single polarization state for a long time and its hysteresis curve moves in a direction along a voltage axis. A ferroelectric capacitor having the imprint effect has a relaxation characteristic that is different than its relaxation characteristic from before the imprint effect occurred according to the direction of movement. In other words, a relaxation amount is reduced in conformity with the movement of the hysteresis curve toward the left, changing a reference voltage of the reference cell, thus reducing the reliability of device during a read operation.
A need therefore exists for a reference voltage generating apparatus and a driving method therefore for providing a stabilized reference voltage and that reduces a relaxation effect or an imprint effect in a ferroelectric capacitor in a reference cell.